In general, bipolar power semiconductors, such as diodes, thyristors, gate turn-off thyristors (GTOs) and gate controlled thyristors (GCTs), are made from silicon wafers. After these silicon wafers have undergone different implantation, diffusion, photolithographic and metallization processes, they are cut to circular discs, and a negative or positive bevel is ground on the high-voltage blocking pn-junction(s). These bevels usually need to be protected with an electric passivation layer. One of the known passivation materials is amorphous hydrogenated carbon (a-C:H, also known as Diamond-like carbon DLC) which can be deposited in a Plasma Enhanced Chemical Vapor Deposition (PECVD) process inside a parallel plate plasma reactor, but could generally be deposited in PECVD reactors of other geometries or by ion beam, sputtering, cathodic arc, pulsed laser deposition or low pressure CVD.
A simplified representation of the general PECVD process is given in FIG. 1. The silicon wafer (substrate) 4 is in contact with the second, lower electrode 2 inside the reaction chamber 8 via a substrate carrier plate 3. A hydrocarbon precursor gas (e.g., methane, acetylene) enters the reaction chamber 8 of the plasma reactor through openings 11 in the first, upper electrode 1, is ionized by radiofrequency, and forms the bulk plasma 6. The edge plasma layer 7 is the space where the plasma ions get accelerated into the direction of the substrate and substrate carrier plate 3 due to a DC bias voltage applied between the two electrodes 1, 2.
The common process is to put the silicon wafers 4 inside a recess 33 on an aluminum substrate carrier plate 3, as depicted in FIG. 1. This substrate carrier plate 3 not only acts as a holder for the silicon wafers (substrate) 4, but it also establishes the disc's thermal and electrical contacts to the actively cooled second (lower) electrode 2 in the reaction chamber 8. The bevel on the silicon wafer facing the first (upper) electrode 1 is exposed to the a-C:H depositing plasma while the remaining upper surface of the silicon wafer 4 is covered by an aluminum shadow mask 5. Active cooling of the silicon wafer 4 during the depositing process is necessary to avoid passivation layers with unsatisfactory electrical properties. Thermal degradation of a-C:H is reported in “Diamond-like amorphous carbon”, by J. Robertson, Materials Science and Engineering: R: Reports 37, (2002) 129.
Silicon wafers with two high voltage blocking pn-junctions (e.g., a thyristor) may have one negative bevel ground on each of its opposite sides. With the common process described above, only the upper bevel is coated with a-C:H in a single process run. As a result, manual flipping-over of the silicon wafer and a second a-C:H deposit-process run are required. Since the bevel coated in the second process step is put into the recess face-down during the first process step in an unprotected and very sensitive state, there is a risk of the bevel becoming contaminated, resulting in a reduced blocking yield.